? semiconductor components industries, llc, 2016 june, 2016 ? rev. 1 1 publication order number: n24c02/d n24c02, n24c04, n24c08, n24c16 2-kb, 4-kb, 8-kb and 16-kb i 2 c cmos serial eeprom description the n24c02/04/08/16 are 2?kb, 4?kb, 8?kb and 16?kb respectively cmos serial eeprom devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. all devices support the standard (100 khz), fast (400 khz) and fast?plus (1 mhz) i 2 c protocol. data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a page write buffer, and then writing all data to non?volatile memory in one internal write cycle. data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count. external address pins make it possible to address up to eight n24c02, four n24c04, two n24c08 and one n24c16 device on the same bus. features ? supports standard, fast and fast?plus i 2 c protocol ? 1.7 v / 1.6 v to 5.5 v supply voltage range ? 16?byte page write buffer ? fast write time (4 ms max) ? hardware write protection for entire memory ? schmitt triggers and noise suppression filters on i 2 c bus inputs (scl and sda) ? low power cmos technology ? more than 1,000,000 program/erase cycles ? 100 year data retention ? industrial and automotive grade 1 temperature range ? us 8?lead package ? these devices are pb?free, halogen free/bfr free and are rohs compliant sda scl wp v cc v ss 1 2 3 4 8 7 6 5 n24c__ 16 / 08 / 04 / 02 nc /// nc nc nc nc nc a 0 a 1 a 1 a 2 a 2 a 2 /// /// pin configuration us8 (u) (top view) www. onsemi.com us8 u suffix case 493 marking diagram see detailed ordering, marking and shipping information in the package dimensions section on page 10 of this data sheet. ordering information xx = specific device code* m = date code = pb?free package 1 8 xx m (note: microdot may be in either location) * see ordering information section for the specific device marking code
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 2 scl wp n24cxx figure 1. functional symbol v ss sda v cc a 2 , a 1 , a 0 table 1. pin function pin name function a0, a1, a2 device address input sda serial data input/output scl serial clock input wp write protect input v cc power supply v ss ground nc no connect table 2. absolute maximum ratings parameters ratings units storage temperature ?65 to +150 c voltage on any pin with respect to ground (note 1) ?0.5 to +6.5 v stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. during input transitions, voltage undershoot on any pin should not exceed ?1 v for more than 20 ns. voltage overshoot on pins a 0 , a 1 , a 2 and wp should not exceed v cc + 1 v for more than 20 ns, while voltage on the i 2 c bus pins, scl and sda, should not exceed the absolute maximum ratings, irrespective of v cc . table 3. reliability characteristics symbol parameter min units n end (note 2) endurance 1,000,000 write cycles (note 3) t dr (note 2) data retention 100 years 2. t a = 25 c 3. a write cycle refers to writing a byte or a page. table 4. d.c. operating characteristics (v cc = 1.7 v / 1.6 v* to 5.5 v, t a = ?40 c to +85 c and v cc = 1.8 v to 5.5 v, t a = ?40 c to +125 c, unless otherwise speci?ed.) symbol parameter test conditions min max units i ccr read current read, f scl = 1 mhz 0.3 ma i ccw write current write 0.5 ma i sb standby current all i/o pins at gnd or v cc t a = ?40 c to +85 c 1 a t a = ?40 c to +125 c 2 i l i/o pin leakage pin at gnd or v cc 2 a v il1 input low voltage 2.2 v v cc 5.5 v ?0.5 0.3 v cc v v il2 input low voltage 1.6 v v cc < 2.2 v ?0.5 0.2 v cc v v ih1 input high voltage 2.2 v v cc 5.5 v 0.7 v cc v cc + 0.5 v v ih2 input high voltage 1.6 v v cc < 2.2 v 0.8 v cc v cc + 0.5 v v ol1 output low voltage v cc 2.2 v, i ol = 6.0 ma 0.4 v v ol2 output low voltage v cc < 2.2 v, i ol = 2.0 ma 0.2 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. *v cc(min) = 1.6 v for read operations, t a = ?20 c to +85 c.
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 3 table 5. pin impedance characteristics (v cc = 1.7 v / 1.6 v* to 5.5 v, t a = ?40 c to +85 c and v cc = 1.8 v to 5.5 v, t a = ?40 c to +125 c, unless otherwise speci?ed.) symbol parameter conditions max units c in (note 4) sda i/o pin capacitance v in = 0 v 8 pf c in (note 4) input capacitance (other pins) v in = 0 v 6 pf i wp , i a (note 5) wp input current, address input current (a0, a1, a2) v in < v ih , v cc = 5.5 v 50 a v in < v ih , v cc = 3.3 v 35 v in < v ih , v cc = 1.7 v 25 v in > v ih 2 4. these parameters are tested initially and after a design or process change that affects the parameter according to appropriat e aec?q100 and jedec test methods. 5. when not driven, the wp, a0, a1 and a2 pins are pulled down to gnd internally. for improved noise immunity, the internal pull ?down is relatively strong; therefore the external driver must be able to supply the pull?down current when attempting to drive the input high. to conserve power, as the input level exceeds the trip point of the cmos input buffer (~ 0.5 x v cc ), the strong pull?down reverts to a weak current source. *v cc(min) = 1.6 v for read operations, t a = ?20 c to +85 c. table 6. a.c. characteristics (v cc = 1.7 v / 1.6 v* to 5.5 v, t a = ?40 c to +85 c and v cc = 1.8 v to 5.5 v, t a = ?40 c to +125 c, unless otherwise speci?ed.) (note 6) symbol parameter standard fast fast?plus units min max min max min max f scl clock frequency 100 400 1,000 khz t hd:sta start condition hold time 4 0.6 0.26 s t low low period of scl clock 4.7 1.3 0.50 s t high high period of scl clock 4 0.6 0.26 s t su:sta start condition setup time 4.7 0.6 0.26 s t hd:dat data in hold time 0 0 0 s t su:dat data in setup time 250 100 50 ns t r (note 7) sda and scl rise time 1,000 300 120 ns t f (note 7) sda and scl fall time 300 300 120 ns t su:sto stop condition setup time 4 0.6 0.26 s t buf bus free time between stop and start 4.7 1.3 0.5 s t aa scl low to data out valid 3.5 0.9 0.45 s t dh (note 7) data out hold time 100 100 50 ns t i (note 7) noise pulse filtered at scl and sda inputs 50 50 50 ns t su:wp wp setup time 0 0 0 s t hd:wp wp hold time 2.5 2.5 1 s t wr write cycle time 4 4 4 ms t pu (notes 7, 8) power-up to ready mode 0.35 0.35 0.35 ms 6. test conditions according to ?a.c. test conditions? table. 7. tested initially and after a design or process change that affects this parameter. 8. t pu is the delay between the time v cc is stable and the device is ready to accept commands. *v cc(min) = 1.6 v for read operations, t a = ?20 c to +85 c. table 7. a.c. test conditions input levels 0.2 x v cc to 0.8 x v cc for v cc 2.2 v 0.15 x v cc to 0.85 x v cc for v cc < 2.2 v input rise and fall times 50 ns input reference levels 0.3 x v cc , 0.7 x v cc output reference levels 0.3 x v cc , 0.7 x v cc output load current source: i ol = 6 ma (v cc 2.2 v); i ol = 2 ma (v cc < 2.2 v); c l = 100 pf
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 4 power?on reset (por) each n24cxx* incorporates power?on reset (por) circuitry which protects the internal logic against powering up in the wrong state. a n24cxx device will power up into standby mode after v cc exceeds the por trigger level and will power down into reset mode when v cc drops below the por trigger level. this bi?directional por feature protects the device against ?brown?out? failure following a temporary loss of power. *for common features, the n24c02/04/08/16 will be referred to as n24cxx. pin description scl : the serial clock input pin accepts the serial clock generated by the master. sda : the serial data i/o pin receives input data and transmits data stored in eeprom. in transmit mode, this pin is open drain. data is acquired on the positive edge, and is delivered on the negative edge of scl. a0, a1 and a2 : the address inputs set the device address when cascading multiple devices. when not driven, these pins are pulled low internally. wp : the write protect input pin inhibits all write operations, when pulled high. when not driven, this pin is pulled low internally. functional description the n24cxx supports the inter?integrated circuit (i 2 c) bus data transmission protocol, which defines a device that sends data to the bus as a transmitter and a device receiving data as a receiver. data flow is controlled by a master device, which generates the serial clock and all start and stop conditions. the n24cxx acts as a slave device. master and slave alternate as either transmitter or receiver. i 2 c bus protocol the i 2 c bus consists of two ?wires?, scl and sda. the two wires are connected to the v cc supply via pull?up resistors. master and slave devices connect to the 2?wire bus via their respective scl and sda pins. the transmitting device pulls down the sda line to ?transmit? a ?0? and releases it to ?transmit? a ?1?. data transfer may be initiated only when the bus is not busy (see ac characteristics). during data transfer, the sda line must remain stable while the scl line is high. an sda transition while scl is high will be interpreted as a start or stop condition (figure 2). the start condition precedes all commands. it consists of a high to low transition on sda while scl is high. the start acts as a ?wake?up? call to all receivers. absent a start, a slave will not respond to commands. the stop condition completes all commands. it consists of a low to high transition on sda while scl is high. note: the i/o pins of n24cxx do not obstruct the scl and sda lines if the vcc supply is switched off. during power?up, the scl and sda pins (connected with pull?up resistors to vcc) will follow the vcc monotonically from vss (0 v) to nominal vcc value, regardless of pull?up resistor value. the delta between the vcc and the instantaneous voltage levels during power ramping will be determined by the relation between bus time constant (determined by pull?up r esistance and bus capacitance) and actual vcc ramp rate. device addressing the master initiates data transfer by creating a start condition on the bus. the master then broadcasts an 8?bit serial slave address. for normal read/write operations, the first 4 bits of the slave address are fixed at 1010 (ah). the next 3 bits are used as programmable address bits when cascading multiple devices and/or as internal address bits. the last bit of the slave address, r/w, specifies whether a read (1) or write (0) operation is to be performed. the 3 address space extension bits are assigned as illustrated in figure 3. a 2 , a 1 and a 0 must match the state of the external address pins, and a 10 , a 9 and a 8 are internal address bits. acknowledge after processing the slave address, the slave responds with an acknowledge (ack) by pulling down the sda line during the 9th clock cycle (figure 4). the slave will also acknowledge the address byte and every data byte presented in write mode. in read mode the slave shifts out a data byte, and then releases the sda line during the 9 th clock cycle. as long as the master acknowledges the data, the slave will continue transmitting. the master terminates the session by not acknowledging the last data byte (noack) and by issuing a stop condition. bus timing is illustrated in figure 5.
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 5 start condition stop condition sda scl figure 2. start/stop timing 1010 a 10 a 9 a 8 r/w n24c16 1010 a 2 a 9 a 8 r/w n24c08 1010 a 2 a 1 a 8 r/w n24c04 1010 a 2 a 1 a 0 r/w n24c02 figure 3. slave address bits 189 start scl from master bus release delay (transmitter) bus release delay (receiver) data output from transmitter data output from receiver ack delay ( t aa ) ack setup ( t su:dat ) figure 4. acknowledge timing figure 5. bus timing scl sda in sda out t su:sta t hd:sta t hd:dat t f t low t aa t high t low t r t dh t buf t su:dat t su:sto
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 6 write operations byte write in byte write mode, the master sends the start condition and the slave address with the r/w bit set to zero to the slave. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the n24cxx. after receiving another acknowledge from the slave, the master transmits the data byte to be written into the addressed memory location. the n24cxx device will acknowledge the data byte and the master generates the stop condition, at which time the device begins its internal write cycle to nonvolatile memory (figure 6). while this internal cycle is in progress (t wr ), the sda output will be tri?stated and the n24cxx will not respond to any request from the master device (figure 7). page write the n24cxx writes up to 16 bytes of data in a single write cycle, using the page write operation (figure 8). the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the data byte is transmitted, the master is allowed to send up to fifteen additional bytes. after each byte has been transmitted the n24cxx will respond with an acknowledge and internally increments the four low order address bits. the high order bits that define the page address remain unchanged. if the master transmits more than sixteen bytes prior to sending the stop condition, the address counter ?wraps around? to the beginning of page and previously transmitted data will be overwritten. once all sixteen bytes are received and the stop condition has been sent by the master, the internal write cycle begins. at this point all received data is written to the n24cxx in a single write cycle. acknowledge polling the acknowledge (ack) polling routine can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host?s write operation, the n24cxx initiates the internal write cycle. the ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the n24cxx is still busy with the write operation, noack will be returned. if the n24cxx has completed the internal write operation, an ack will be returned and the host can then proceed with the next read or write operation. hardware write protection with the wp pin held high, the entire memory is protected against write operations. if the wp pin is left floating or is grounded, it has no impact on the operation of the n24cxx. the state of the wp pin is strobed on the last falling edge of scl immediately preceding the first data byte (figure 9). if the wp pin is high during the strobe interval, the n24cxx will not acknowledge the data byte and the write request will be rejected. delivery state the n24cxx is shipped erased, i.e., all bytes are ffh. address byte data byte slave address s a c k a c k a c k s t o p p s t a r t bus activity: master slave a 7 ? a 0 d 7 ? d 0 figure 6. byte write sequence
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 7 t wr stop condition start condition address ack 8 th bit byte n scl sda figure 7. write cycle timing a c k a c k a c k s t o p s a c k a c k s t a r t p slave address n = 1 p 15 address byte n n+1 n+p bus activity: master slave data byte data byte data byte figure 8. page write sequence 1891 8 a 7 a 0 d 7 d 0 t su:wp t hd:wp address byte data byte scl sda wp figure 9. wp timing
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 8 read operations immediate read upon receiving a slave address with the r/w bit set to ?1?, the n24cxx will interpret this as a request for data residing at the current byte address in memory. the n24cxx will acknowledge the slave address, will immediately shift out the data residing at the current address, and will then wait for the master to respond. if the master does not acknowledge the data (noack) and then follows up with a stop condition (figure 10), the n24cxx returns to standby mode. selective read selective read operations allow the master device to select at random any memory location for a read operation. the master device first performs a ?dummy? write operation by sending the start condition, slave address and byte address of the location it wishes to read. after the n24cxx acknowledges the byte address, the master device resends the start condition and the slave address, this time with the r/w bit set to one. the n24cxx then responds with its acknowledge and sends the requested data byte. the master device does not acknowledge the data (noack) but will generate a stop condition (figure 11). sequential read if during a read session, the master acknowledges the 1 st data byte, then the n24cxx will continue transmitting data residing at subsequent locations until the master responds with a noack, followed by a stop (figure 12). in contrast to page w rite, during sequential read the address count will automatically increment to and then wrap?around at end of memory (rather than end of page). scl sda 8 th bit stop no ack data out 89 slave address s a c k d ata byte n o a c k s t o p p s t a r t bus activity: master slave figure 10. immediate read sequence and timing slave s a c k n o a c k s t o p p s t a r t s a c k slave address a c k s t a r t d ata byte address byte address bus activity: master slave figure 11. selective read sequence s t o p p slave address a c k a c k a c k n o a c k a c k d ata byte n d ata byte n+1 d ata byte n+2 d ata byte n+x bus activity: master slave figure 12. sequential read sequence
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 9 package dimensions us8 case 493 issue d dim a min max min max inches 1.90 2.10 0.075 0.083 millimeters b 2.20 2.40 0.087 0.094 c 0.60 0.90 0.024 0.035 d 0.17 0.25 0.007 0.010 f 0.20 0.35 0.008 0.014 g 0.50 bsc 0.020 bsc h 0.40 ref 0.016 ref j 0.10 0.18 0.004 0.007 k 0.00 0.10 0.000 0.004 l 3.00 3.20 0.118 0.128 m 0 6 0 6 n 0 10 0 10 p 0.23 0.34 0.010 0.013 r 0.23 0.33 0.009 0.013 s 0.37 0.47 0.015 0.019 u 0.60 0.80 0.024 0.031 v 0.12 bsc 0.005 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. dimension a does not include mold flash, protrusion or gate burr. mold flash. protrusion and gate burr shall not exceed 0.14mm (0.0055?) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash and protrusion shall not exceed 0.14mm (0.0055?) per side. 5. lead finish is solder plating with thickness of 0.0076?0.0203mm (0.003?0.008?). 6. all tolerance unless otherwise specified 0.0508mm (0.0002?). l b a p g 4 1 5 8 c k d seating j s r u detail e v f h n r 0.10 typ m detail e t m 0.10 (0.004) xy t 0.10 (0.004) plane x y t 0.30 8x dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.50 recommended 1 pitch 3.40 0.68 8x
n24c02, n24c04, n24c08, n24c16 www. onsemi.com 10 ordering information n24c02 ordering information device order number specific device marking package type temperature range shipping n24c02udtg av u = us?8 d = industrial (?40 c to +85 c) t = tape & reel, 3,000 units / reel n24c02uvtg am u = us?8 v = automotive grade 1 (?40 c to +125 c) t = tape & reel, 3,000 units / reel n24c04 ordering information device order number specific device marking package type temperature range shipping n24c04udtg an u = us?8 d = industrial (?40 c to +85 c) t = tape & reel, 3,000 units / reel n24c04uvtg aw u = us?8 v = automotive grade 1 (?40 c to +125 c) t = tape & reel, 3,000 units / reel n24c08 ordering information device order number specific device marking package type temperature range shipping n24c08udtg ap u = us?8 d = industrial (?40 c to +85 c) t = tape & reel, 3,000 units / reel n24c08uvtg ax u = us?8 v = automotive grade 1 (?40 c to +125 c) t = tape & reel, 3,000 units / reel n24c16 ordering information device order number specific device marking package type temperature range shipping n24c16udtg aq u = us?8 d = industrial (?40 c to +85 c) t = tape & reel, 3,000 units / reel N24C16UVTG az u = us?8 v = automotive grade 1 (?40 c to +125 c) t = tape & reel, 3,000 units / reel 9. all packages are rohs?compliant (lead?free, halogen?free). 10. for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and ree l packaging specifications brochure, brd8011/d. on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 n24c02/d on semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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